Garbage collection in a memory sub-system during a low battery state

ABSTRACT

Systems, apparatuses, and methods related to media management, including “garbage collection,” in memory or storage systems or sub-systems, such as solid state drives, are described. For example, a battery state associated with the memory system or sub-system may be used as an indicator or basis for managing a garbage collection operation on a data block. A controller or the system or sub-system may determine that a battery state or condition satisfies a criterion. Based on determining that the criterion is satisfied the, the garbage collection operation may be postponed until the battery state changes to satisfy a different battery condition.

RELATED APPLICATION

This application claims the benefit of U.S. Provisional Application No.62/889,283, filed Aug. 20, 2019, the entire contents of which are herebyincorporated by reference herein.

TECHNICAL FIELD

Embodiments of the disclosure relate generally to memory sub-systems,and more specifically, relate to garbage collection in a memorysub-system during a low battery state.

BACKGROUND

A memory sub-system can be a storage system, such as a solid-state drive(SSD), or a hard disk drive (HDD). A memory sub-system can be a memorymodule, such as a dual in-line memory module (DIMM), a small outlineDIMM (SO-DIMM), or a non-volatile dual in-line memory module (NVDIMM). Amemory sub-system can include one or more memory components that storedata. The memory components can be, for example, non-volatile memorycomponents and volatile memory components. In general, a host system canutilize a memory sub-system to store data at the memory components andto retrieve data from the memory components.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure will be understood more fully from the detaileddescription given below and from the accompanying drawings of variousembodiments of the disclosure.

FIG. 1 illustrates an example computing environment that includes amemory sub-system in accordance with some embodiments of the presentdisclosure.

FIG. 2 illustrates an example of postponing garbage collection during alow battery state associated with a memory sub-system in accordance withsome embodiments of the present disclosure.

FIG. 3 is a flow diagram of an example method to postpone garbagecollection during a low battery state associated with a memorysub-system in accordance with some embodiments of the presentdisclosure.

FIG. 4 is a flow diagram of an example method to monitor batterycondition associated with a memory sub-system for performing garbagecollection in accordance with some embodiments of the presentdisclosure.

FIG. 5 is a block diagram of an example computer system in whichembodiments of the present disclosure may operate.

DETAILED DESCRIPTION

Aspects of the present disclosure are directed to garbage collection ina memory sub-system including postponing the garbage collection during alow battery state of the memory sub-system. A memory sub-system is alsohereinafter referred to as a “memory device.” An example of a memorysub-system is a storage device that is coupled to a central processingunit (CPU) via a peripheral interconnect (e.g., an input/output bus, astorage area network). Examples of storage devices include a solid-statedrive (SSD), a flash drive, a universal serial bus (USB) flash drive,and a hard disk drive (HDD). Another example of a memory sub-system is amemory module that is coupled to the CPU via a memory bus. Examples ofmemory modules include a dual in-line memory module (DIMM), a smalloutline DIMM (SO-DIMM), a non-volatile dual in-line memory module(NVDIMM), etc. In some embodiments, the memory sub-system can be ahybrid memory/storage sub-system. In general, a host system can utilizea memory sub-system that includes one or more memory components. Thehost system can provide data to be stored at the memory sub-system andcan request data to be retrieved from the memory sub-system.

When the host system requests to store data, the data is stored at aphysical address within the memory component. The host system provides alogical address identifying the data to be stored. A logical to physical(L2P) mapping table is maintained to identify the physical locationwhere the data corresponding to each logical address resides. A memorycomponent in a memory sub-system can include one or more memory pages(also referred to herein as “pages”) for storing one or more bits ofbinary data corresponding to data received from the host system. One ormore memory pages of the memory component can be grouped together toform a data block. When the data is written to the memory component, itis typically done at the page level, such that an entire page, ormultiple pages, is written in a single operation. When the host systemrequests to update data at a particular logical address, the updateddata is stored at a new physical location (e.g., a new physical address)and the L2P mapping is updated so that the particular logical address ofthe data is mapped to the new physical address. The original data (e.g.,the data prior to the update) still remains stored in the originalphysical address. This data, however, is no longer valid from the host'sperspective, and is no longer usable by the host. With various changesin data, the memory component accumulates physical addresses acrossvarious data blocks that have invalid data, in addition to havingphysical addresses with valid data. The invalid data stored at thememory component is considered “garbage” and can be cleaned out at somepoint.

When the memory component is full, such that there is insufficientcapacity to accept data from additional write operations, certain datacan be erased in order to free up space. When data is erased from thememory component, however, it is typically done at the block level, suchthat an entire block (including multiple pages) is erased in a singleoperation. Thus, when a particular segment of data on the memorycomponent is updated, certain pages in a block will have data that hasbeen re-written to a different location and/or is no longer needed. Theentire block cannot simply be erased as each block likely also has somenumber of pages of valid data. A garbage collection (“GC”) process canbe performed which involves migrating (e.g., rewriting) those pages ofthe block that contain valid data to another block, so that the currentblock with both valid and invalid data can be erased. Garbage collectionis a form of automatic memory management that attempts to reclaimgarbage, or memory occupied by stale data objects that are no longer inuse (e.g., because they have been updated with new values). The basicprinciple of garbage collection is to find data objects that cannot orneed not be accessed in the future, and to reclaim the resources (i.e.storage space) used by those objects.

A conventional memory sub-system can include a controller thatdetermines when it is appropriate to initiate a garbage collectionoperation. The controller can perform calculations to determine anoptimum time for performing the GC operation, optimizing for variousfactors. In some examples, GC is initiated periodically as part ofregular memory management operations for the memory sub-system. In otherexamples, GC is initiated in response to a particular event, such as,receiving a write request (e.g., from the host system) and adetermination that memory components have insufficient capacity toaccept the write request. In some examples, the controller can determinethat the memory component is full and/or there is insufficient capacityto accept any other additional write operations that can be receivedfrom the host and that garbage collection needs to be performed to freeup space in the memory component. In some examples, the controller candetermine that the memory sub-system, or certain components within thememory sub-system, is in an idle state or is experiencing downtime andGC can be performed during this time. Based on the determination of theappropriate time, the controller can initiate the garbage collectionoperation to erase invalid data from certain blocks.

At times, the controller can determine to perform GC proactively undervarious circumstances. For example, when the controller determines thatGC will be expected to be performed in the near future, the controllercan perform GC proactively, instead of waiting until when it is urgentto perform GC at which point it can take a significant amount of time toperform the GC operation. That is, the controller can determine that GCcan be performed but performing GC is optional (e.g., system is in idlestate). The GC can be performed in small increments and earlier thanwhen it is absolutely necessary. At other times, the controller candetermine that GC must be performed, so performing the GC is mandatory(e.g., memory component is full). However, GC can be a power intensiveoperation. GC can require complex algorithms to optimize for variousfactors, which may consume significant battery power. If the memorysub-system is already in a low battery state (e.g., battery liferemaining in the system is identified as being low, such as, 10% oftotal battery life), then performing GC during this time can addadditional load on battery usage and diminish the remaining battery lifeearlier than if the GC is not performed.

Aspects of the present disclosure address the above and otherdeficiencies by monitoring battery state associated with the memorysub-system and postponing garbage collection operation when batterystate is identified as being low. In one implementation, a controller ina memory sub-system determines an appropriate time to perform a GCoperation by determining that a criterion is satisfied to perform agarbage collection operation on a memory component of the memorysub-system. A determination can be made as to whether the battery stateassociated with the memory sub-system satisfies a battery condition(e.g., battery life being below a threshold). If the battery conditionis satisfied, the controller can continue to monitor the battery stateand postpone the GC operation, as needed, until the battery statechanges to satisfy another battery condition (e.g., battery life reachesor is above the threshold). If the battery condition is not satisfied(e.g., battery life is not below the threshold), or the battery statechanges to satisfy the other battery condition (e.g., battery life beingabove the threshold), controller can perform the GC operation.

The present disclosure reduces or eliminates the effects of performinggarbage collection operation on battery life when the battery life isconsidered to be already low. Advantages of the present disclosureinclude, but are not limited to, preserving battery life for performingimportant and urgent operations, increased performance of the memorysub-system as competing operations are minimized when using limitedbattery power, not wasting computing resources on performing garbagecollection operations that can be delayed, overall performance of thememory sub-system can be improved as other read or write operations canbe performed by the memory sub-system instead of performing the garbagecollection operation with the limited remaining battery life.

FIG. 1 illustrates an example computing environment 100 that includes amemory sub-system 110 in accordance with some embodiments of the presentdisclosure. The memory sub-system 110 can include media, such as memorycomponents 112A to 112N. The memory components 112A to 112N can bevolatile memory components, non-volatile memory components, or acombination of such. In some embodiments, the memory sub-system is astorage system. An example of a storage system is a SSD. In someembodiments, the memory sub-system 110 is a hybrid memory/storagesub-system. In general, the computing environment 100 can include a hostsystem 120 that uses the memory sub-system 110. For example, the hostsystem 120 can write data to the memory sub-system 110 and read datafrom the memory sub-system 110.

The host system 120 can be a computing device such as a desktopcomputer, laptop computer, network server, mobile device, or suchcomputing device that includes a memory and a processing device. Thehost system 120 can include or be coupled to the memory sub-system 110so that the host system 120 can read data from or write data to thememory sub-system 110. The host system 120 can be coupled to the memorysub-system 110 via a physical host interface. As used herein, “coupledto” generally refers to a connection between components, which can be anindirect communicative connection or direct communicative connection(e.g., without intervening components), whether wired or wireless,including connections such as electrical, optical, magnetic, etc.Examples of a physical host interface include, but are not limited to, aserial advanced technology attachment (SATA) interface, a peripheralcomponent interconnect express (PCIe) interface, universal serial bus(USB) interface, Fibre Channel, Serial Attached SCSI (SAS), etc. Thephysical host interface can be used to transmit data between the hostsystem 120 and the memory sub-system 110. The host system 120 canfurther utilize an NVM Express (NVMe) interface to access the memorycomponents 112A to 112N when the memory sub-system 110 is coupled withthe host system 120 by the PCIe interface. The physical host interfacecan provide an interface for passing control, address, data, and othersignals between the memory sub-system 110 and the host system 120.

The memory components 112A to 112N can include any combination of thedifferent types of non-volatile memory components and/or volatile memorycomponents. An example of non-volatile memory components includes anegative- and (NAND) type flash memory. Each of the memory components112A to 112N can include one or more arrays of memory cells such assingle level cells (SLCs) or multi-level cells (MLCs) (e.g., triplelevel cells (TLCs) or quad-level cells (QLCs)). In some embodiments, aparticular memory component can include both an SLC portion and a MLCportion of memory cells. Each of the memory cells can store one or morebits of data (e.g., data blocks) used by the host system 120. Althoughnon-volatile memory components such as NAND type flash memory aredescribed, the memory components 112A to 112N can be based on any othertype of memory such as a volatile memory. In some embodiments, thememory components 112A to 112N can be, but are not limited to, randomaccess memory (RAM), read-only memory (ROM), dynamic random accessmemory (DRAM), synchronous dynamic random access memory (SDRAM), phasechange memory (PCM), magneto random access memory (MRAM), negative-or(NOR) flash memory, electrically erasable programmable read-only memory(EEPROM), and a cross-point array of non-volatile memory cells. Across-point array of non-volatile memory can perform bit storage basedon a change of bulk resistance, in conjunction with a stackablecross-gridded data access array. Additionally, in contrast to manyflash-based memories, cross-point non-volatile memory can perform awrite in-place operation, where a non-volatile memory cell can beprogrammed without the non-volatile memory cell being previously erased.Furthermore, the memory cells of the memory components 112A to 112N canbe grouped as memory pages or data blocks that can refer to a unit ofthe memory component used to store data.

The memory system controller 115 (hereinafter referred to as“controller”) can communicate with the memory components 112A to 112N toperform operations such as reading data, writing data, or erasing dataat the memory components 112A to 112N and other such operations. Thecontroller 115 can include hardware such as one or more integratedcircuits and/or discrete components, a buffer memory, or a combinationthereof. The controller 115 can be a microcontroller, special purposelogic circuitry (e.g., a field programmable gate array (FPGA), anapplication specific integrated circuit (ASIC), etc.), or other suitableprocessor. The controller 115 can include a processor (processingdevice) 117 configured to execute instructions stored in local memory119. In the illustrated example, the local memory 119 of the controller115 includes an embedded memory configured to store instructions forperforming various processes, operations, logic flows, and routines thatcontrol operation of the memory sub-system 110, including handlingcommunications between the memory sub-system 110 and the host system120. In some embodiments, the local memory 119 can include memoryregisters storing memory pointers, fetched data, etc. The local memory119 can also include read-only memory (ROM) for storing micro-code.While the example memory sub-system 110 in FIG. 1 has been illustratedas including the controller 115, in another embodiment of the presentdisclosure, a memory sub-system 110 may not include a controller 115,and may instead rely upon external control (e.g., provided by anexternal host, or by a processor or controller separate from the memorysub-system).

In general, the controller 115 can receive commands or operations fromthe host system 120 and can convert the commands or operations intoinstructions or appropriate commands to achieve the desired access tothe memory components 112A to 112N. The controller 115 can beresponsible for other operations such as wear leveling operations,garbage collection operations, error detection and error-correcting code(ECC) operations, encryption operations, caching operations, and addresstranslations between a logical block address and a physical blockaddress that are associated with the memory components 112A to 112N. Thecontroller 115 can further include host interface circuitry tocommunicate with the host system 120 via the physical host interface.The host interface circuitry can convert the commands received from thehost system into command instructions to access the memory components112A to 112N as well as convert responses associated with the memorycomponents 112A to 112N into information for the host system 120.

The memory sub-system 110 can also include additional circuitry orcomponents that are not illustrated. In some embodiments, the memorysub-system 110 can include a cache or buffer (e.g., DRAM) and addresscircuitry (e.g., a row decoder and a column decoder) that can receive anaddress from the controller 115 and decode the address to access thememory components 112A to 112N.

The memory sub-system 110 includes a battery monitoring component 113that can be used to store data at a particular memory component based ona corresponding usage threshold. In some embodiments, the controller 115includes at least a portion of the battery monitoring component 113. Forexample, the controller 115 can include a processor 117 (processingdevice) configured to execute instructions stored in local memory 119for performing the operations described herein. In some embodiments, thebattery monitoring component 113 is part of the host system 120, anapplication, or an operating system.

The battery monitoring component 113 can receive an indication fromcontroller 115 that a criterion to perform a garbage collectionoperation is satisfied where the garbage collection operation is to beperformed on memory components 112A to 112N of the memory sub-system110. The battery monitoring component 113 can determine that a batterystate of a memory sub-system 110 satisfies a first battery condition(e.g., the battery state being below a threshold battery life) andindicate to the controller to postpone the garbage collection operationuntil the battery state changes to satisfy a second battery condition(e.g., the battery state reaching or going above the threshold batterylife). Further details with regards to the operations of the batterymonitoring component 113 are described below.

FIG. 2 illustrates an example of postponing garbage collection operationduring a low battery state associated with a memory sub-system 200 inaccordance with some embodiments of the present disclosure. In general,the memory sub-system 200 can correspond to the memory sub-system 110 ofFIG. 1. For example, the memory sub-system 200 can include batterymonitoring component 113 of FIG. 1. In some embodiments, the batterymonitoring component 113 can be configured to monitor a battery stateassociated with the memory sub-system 200 and to determine whether toperform or postpone a garbage collection operation based on the batterystate associated with memory sub-system 200.

Controller 115 can set various garbage collection levels 210. Thegarbage collection levels can indicate the level of necessity to performthe GC operation. In one example, the level of necessity can bedetermined by factors, such as, amount of invalid data on the datablock. For example, level 212 can indicate that garbage collection isnot necessary; level 214 can indicate that garbage collection can beperformed proactively (e.g., optionally) but it is not mandatory (e.g.,not urgent); and level 216 can indicate that performing garbagecollection is mandatory (e.g., urgent). Controller 115 can performcalculations to determine an optimum time for performing the GCoperation based on policies set in controller 115, optimizing forvarious factors (e.g., sequential write, dirty condition, etc.). Basedon the calculations, controller 115 can determine whether one of thegarbage collection levels 210 is satisfied.

In one example, controller 115 can make the determination for an optimumtime for performing the GC operation based on capacity to acceptadditional write operations from host 120. As shown in the example ofFIG. 2, memory component 112 can include a number of memory cells (e.g.,C1 to Cn). Each of the memory cells can store one or more bits of binarydata corresponding to data received from the host system 120. Separatedata blocks (e.g., B1, B2, Bn, etc.) in the memory component 112 can beformed by grouping the memory cells together. In an example, controller115 can determine that memory component 112 is in a clean condition,that is, the level of invalid data across various data blocks B1 throughBn is below a threshold set for performing GC operations. In thatsituation, controller 115 can determine that that a GC operation is notnecessary, and that level 212 is satisfied. If level 212 is satisfied,the controller 115 does not perform GC.

In an example, such as that shown in FIG. 2, memory cells C1, C3, C4,C7, and C8 of data block B1 contain invalid data and memory cells C2,C5, and C6 of data block B1 contain valid data. Controller 115 candetermine that data block B1 will be too “dirty” (e.g., contain too muchinvalid data) in the near future, or after some of the cells C2, C5, andC6 contain invalid data. In conjunction with assessing capacity of otherdata blocks B2 through Bn, controller 115 can determine that memorycomponent 112 is becoming full such that there will be insufficientcapacity for accepting write operations from host 120 within apredetermined time frame or a number of operations in the future. Inthis situation, controller 115 can determine that a garbage collectionoperation can be initiated proactively (e.g., optionally) to clean upthe memory component 112, instead of waiting until when the memorycomponent 112 is in too dirty condition. Controller 115 can determinethat level 214 is satisfied, that is, GC can be performed proactively(e.g., optionally) but it is not mandatory (e.g., not urgent) to performthe GC operation. In an example, GC level 214 indicates that the amountof invalid data on the data block is at a level where the GC operationcan be optionally performed. As a result, controller 115 determines thata criterion to perform the GC operation is satisfied. Controller 115performs the GC operation by writing data from memory cells C1, C3, C4,C7, and C8 of data block B1 to memory cells in one or more other datablocks, and erasing the data from data block B1 to reclaim the memoryspace.

In one implementation, battery monitoring component 113 can receive anindication from controller 115 that a criterion to perform a garbagecollection operation is satisfied in response to garbage collectionlevel 214 being satisfied. That is, the controller 115 can determinethat the GC operation can be performed proactively but it is notmandatory (e.g., urgent) to perform the GC operation.

Upon receiving indication that the criterion to perform a garbagecollection operation is satisfied, battery monitoring component 113 candetermine whether a battery state associated with the memory sub-system200 satisfies a first battery condition. In some examples, the batterystate can indicate the remaining battery life associated with the memorysub-system 200 at a certain point in time. In an example, the batterystate can indicate there is 30% battery life remaining out of a total of100% battery life. In some other examples, the battery state canindicate the memory sub-system is associated with low battery, averagebattery, high battery, full battery, etc.

Battery state associated with the memory component 112 can be obtainedin various ways. In one example, the battery state can include a batterystate 242 obtained from one or more battery sensors 240 within computingenvironment 100. In another example, controller 115 can provide batterystate 242. In yet another example, host 120 can provide battery state242. In some examples, a signal from one of the components associatedwith the memory sub-system 200 can indicate battery state 242. In someimplementations, battery state 242 can be obtained periodically and atpredefined intervals and be provided to battery monitoring component113. In other implementations, the battery sensors 240 can provide thebattery state 242 responsive to one or more commands or queries, such asa particular command by battery monitoring component 113 to obtainbattery state 242.

Battery monitoring component 113 can perform a battery comparisonoperation using a comparator 220 to determine whether the battery stateassociated with the memory sub-system 200 satisfies a battery condition.In an example, a battery condition can be defined as the battery statebeing below, equal to, or above a threshold battery life. As shown inFIG. 2, the memory sub-system 200 can specify one or more thresholdbattery lives, a first threshold battery life B_(Th1) 222 and/or asecond threshold battery B_(Th2) 223. In another example, a batterycondition can be defined as the battery state being low battery, not lowbattery, full battery, etc.

In an implementation, comparator 220 can determine whether the batterystate associated with memory sub-system 200 satisfies a first batterycondition. In an example, the first battery condition can be defined asthe battery state being below the first threshold battery life B_(Th1)222 (e.g., 15% of total battery life) as specified in the memorysub-system 200. FIG. 2 shows a battery state B_(st) 224 (e.g., 14% oftotal battery life) at one point in time. Comparator 220 can compare thefirst threshold battery life B_(Th1) 222 and the battery state B_(st)224. The comparator 220 can determine that the battery state B_(st) 224is below the first threshold battery life B_(Th1) 222. In anotherexample, the first battery condition can be defined as the battery statebeing low battery.

If it is determined that battery state B_(st) 224 satisfies the firstbattery condition, controller 115 can postpone the GC operation. The GCoperation can be postponed despite the determination that the criterionto perform the GC operation is satisfied. In one example, controller 115can postpone the GC operation by not performing the GC operation. Inanother example, postponing the GC operation can be achieved bycontinuing to monitor the battery state to detect changes in the batterystate without performing the GC operation. By excluding performance ofthe power intensive GC operation when battery state is determined asbeing below the threshold, or as being low battery, the remaininglimited battery life can be preserved for performing other urgentoperations and/or to extend the battery life for longer period than ifGC was to be performed.

In some embodiments, controller 115 can postpone the GC operation untilthe battery state changes to satisfy a second battery condition. Thecomparator 220 can determine that the battery state has changed tosatisfy the second battery condition. In an example, the second batterycondition can be defined as the battery state being equal to or abovethe first threshold battery life B_(Th1) 222 (e.g., 15% of total batterylife) as specified in the memory sub-system 200. In one example, aftercontinuing to monitor the battery state, the battery state can change togo further below the first threshold battery life B_(Th1) 222 than thebattery state B_(st) 224 previously obtained. In this case, the secondbattery condition is not satisfied and battery monitoring component 113can continue to monitor the battery state. In another example, thebattery state can change to reach or surpass the first threshold batterylife B_(Th1) 222 to be B_(st) 226. In this case, battery state B_(st)226 satisfies the second battery condition of being equal to or abovethe first threshold battery life. The comparator 220 can determine thatB_(st) 226 is equal to or above the first threshold battery life B_(Th1)222. In another example, the second battery condition can be defined asthe battery state being above a second threshold battery life B_(Th1)223 (e.g., 20% of total battery life) (not shown) that is different fromthe first threshold battery life B_(Th1) 222. In such examples, adifference between the first and the second threshold battery life canbe used to make certain that performing GC operation does notimmediately bring the battery state to be in a low battery state. Insome examples, the second battery condition can be defined as thebattery state being not low battery, or being one of average battery,high battery, or full battery. Upon battery monitoring component 113determining that the battery state changed to satisfy the second batterycondition, controller 115 can perform the GC operation. By performingthe GC operation 250 after battery state changes to be equal to or abovethe threshold battery life, the power intensive GC operation isperformed when there is adequate battery life to support the operation.

In some examples, upon receiving indication that the criterion toperform a garbage collection operation is satisfied, battery monitoringcomponent 113 can determine that the battery state does not satisfy thefirst battery condition. That is, comparator 220 can determine thatbattery state B_(st) 226 is equal to or above the first thresholdbattery B_(Th1) 222. In that situation, controller 115 performs the GCoperation 250. For example, controller 115 performs the GC operation bymigrating data from memory cell C2, C5, and C6 of data block B1 tomemory cells in other data block(s), such as data block B2.

In some examples (not shown), controller 115 can determine that memorycomponent 112 is too dirty, and cannot accept additional writeoperations from host 120, thus determine that level 216 is satisfied(e.g., GC is mandatory). That is, GC level 216 can indicate that theamount of invalid data on the data block is at a level where the GCoperation must be performed. In one example, this determination can bemade before determining that the battery state satisfies a first batterycondition (e.g., low battery, below threshold battery life, etc.), orafter determining that the battery state satisfies the first batterycondition but prior to the battery state changing to satisfy the secondbattery condition (e.g., not low battery). Upon determining that level216 is satisfied, that is, GC operation is urgent, controller 115determines that a criterion to perform the GC operation is satisfied.

In some implementation, if level 216 is satisfied (e.g., GC is urgent),then even if battery state indicates low batter life, controller 115performs the GC operation. Controller 115 performs the GC operationregardless of battery state in order to accept additional host writeoperations without a failure. In other implementations, batterymonitoring component 113 can consider various factors to determinewhether the GC operation that is indicated as urgent is to be performedwhen battery state indicates low battery life. For example, the factorscan include, but are not limited to, level of importance of continuingother operations that are being performed at the time and whether thoseoperations have to be suspended, whether failure to accept writeoperation is indicated as being more or less important than preservingbattery life, other factors assessing importance of battery lifepreservation against garbage collection, etc. Based on the factors, inone example, battery monitoring component 113 can indicate to thecontroller 115 to postpone the GC operation despite level 216 beingsatisfied.

FIG. 3 is a flow diagram of an example method 300 to postpone garbagecollection during a low battery state associated with a memorysub-system, in accordance with some embodiments of the presentdisclosure. The method 300 can be performed by processing logic that caninclude hardware (e.g., processing device, circuitry, dedicated logic,programmable logic, microcode, hardware of a device, integrated circuit,etc.), software (e.g., instructions run or executed on a processingdevice), or a combination thereof. In some embodiments, the method 300is performed by the battery monitoring component 113 of FIG. 1. Althoughshown in a particular sequence or order, unless otherwise specified, theorder of the processes can be modified. Thus, the illustratedembodiments should be understood only as examples, and the illustratedprocesses can be performed in a different order, and some processes canbe performed in parallel. Additionally, one or more processes can beomitted in various embodiments. Thus, not all processes are required inevery embodiment. Other process flows are possible.

At operation 310, the processing logic determines that a criterion toperform a garbage collection operation is satisfied. In animplementation, the processing logic can determine that the criterion toperform GC operation is satisfied in response to determining that afirst garbage collection level to perform the garbage collectionoperation is satisfied. In an example, the first garbage collectionlevel indicates that the garbage collection operation can be performedproactively (e.g., GC can be performed but not urgent to be performed).

At operation 320, the processing logic determines whether a batterystate associated with the memory sub-system satisfies a first batterycondition. In an example, the first battery condition is satisfied whenthe battery state is below a first threshold battery life. In anotherexample, the first battery condition is satisfied when the battery stateindicates low battery life.

If the battery state satisfies the first battery condition, at operation330, the processing logic postpones the garbage collection operationuntil the battery state changes to satisfy a second battery condition.The GC operation can be postponed despite the criterion to perform GCoperation being satisfied. In one example, the processing logic canpostpone the GC operation by not performing the GC operation. In anexample, the battery state satisfies the second battery condition whenthe battery state changes to be equal to or above a second thresholdbattery life. In some examples, the second threshold battery life is thesame as the first threshold battery life. In other examples, the secondthreshold battery life is different from the first threshold batterylife.

If the battery state does not satisfy the first battery condition, atoperation 340, the processing logic performs the garbage collectionoperation. For example, battery state Bst 226 can indicate that memorysub-system 200 is not associated with low battery, or is not below thefirst threshold battery life B_(TH1) 222 at a certain point in time. Inanother example, even if battery state initially satisfied the firstbattery condition (e.g., battery state was below the threshold at onepoint), the processing logic can determine that the battery statechanged to satisfy the second battery condition (e.g., battery stateequal to or above the threshold condition). In such scenarios,processing logic performs the GC operation 250.

The processing logic can further determine that a second garbagecollection level to perform the garbage collection operation issatisfied prior to the battery state changing to satisfy the secondbattery condition. For example, the second garbage collection levelindicates that performing the garbage collection operation is mandatory(e.g., “urgent”). Responsive to the second garbage collection conditionlevel being satisfied, the processing logic can perform the garbagecollection operation.

FIG. 4 is a flow diagram of an example method 400 to monitor batterycondition associated with a memory sub-system for performing garbagecollection, in accordance with some embodiments of the presentdisclosure. The method 400 can be performed by processing logic that caninclude hardware (e.g., processing device, circuitry, dedicated logic,programmable logic, microcode, hardware of a device, integrated circuit,etc.), software (e.g., instructions run or executed on a processingdevice), or a combination thereof. In some embodiments, the method 400is performed by the battery monitoring component 113 of FIG. 1. Althoughshown in a particular sequence or order, unless otherwise specified, theorder of the processes can be modified. Thus, the illustratedembodiments should be understood only as examples, and the illustratedprocesses can be performed in a different order, and some processes canbe performed in parallel. Additionally, one or more processes can beomitted in various embodiments. Thus, not all processes are required inevery embodiment. Other process flows are possible.

At operation 410, the processing logic determines that a criterion toperform a garbage collection operation is satisfied. In animplementation, processing logic can determine that the criterion toperform GC operation is satisfied in response to determining that afirst GC level to perform the garbage collection operation is satisfied.In an example, the first GC level indicates that the garbage collectionoperation can be performed proactively (e.g., optional but not urgent).

At operation 420, the processing logic monitors a battery stateassociated with the memory sub-system. In some examples, the batterystate can indicate the remaining battery life associated with the memorysub-system 200 at a certain point in time. In some other examples, thebattery state can indicate the memory sub-system is associated with lowbattery, average battery, high battery, full battery, etc. at a certaintime.

At operation 430, the processing logic determines whether the batterystate satisfies a first battery condition. In an example, the firstbattery condition is satisfied when the battery state is below a firstthreshold battery life. In another example, the first battery conditionis satisfied when the battery state indicates low battery life.

If the battery state satisfies the first battery condition, theprocessing logic repeats operation 420 to continue to monitor thebattery state to detect changes in the battery state satisfying a secondbattery condition. In an example, the second battery condition issatisfied when the battery state is equal to or above a second thresholdbattery life. In some embodiments, the first threshold battery life issame as the second threshold battery life, and in other embodiments, thefirst threshold battery life is different from the second thresholdbattery life. In another example, the second battery condition issatisfied when the battery state does not indicate low battery life. Inan example, the processing logic can continue to monitor the batterystate without performing the GC operation. By continuing to monitor thebattery state without performing the GC until the second batterycondition is satisfied, the processing logic postpones the GC operationuntil the second battery condition is satisfied.

If the battery state does not satisfy the first battery condition (e.g.,remaining battery life is not low), at operation 440, the processinglogic performs the GC operation. In one example, battery state Bst 226can indicate that memory sub-system 200 is not associated with lowbattery, or is not below the first threshold battery life B_(TH1) 222 ata certain point in time. In another example, even if battery stateinitially satisfied the first battery condition (e.g., low battery stateat one point), the processing logic can determine that the battery statechanged to satisfy the second battery condition (e.g., battery stateequal to or above the threshold condition). In such scenarios,processing logic performs the GC operation 250.

FIG. 5 illustrates an example machine of a computer system 500 withinwhich a set of instructions, for causing the machine to perform any oneor more of the methodologies discussed herein, can be executed. In someembodiments, the computer system 500 can correspond to a host system(e.g., the host system 120 of FIG. 1) that includes, is coupled to, orutilizes a memory sub-system (e.g., the memory sub-system 110 of FIG. 1)or can be used to perform the operations of a controller (e.g., toexecute an operating system to perform operations corresponding to thebattery monitoring component 113 of FIG. 1). In alternative embodiments,the machine can be connected (e.g., networked) to other machines in aLAN, an intranet, an extranet, and/or the Internet. The machine canoperate in the capacity of a server or a client machine in client-servernetwork environment, as a peer machine in a peer-to-peer (ordistributed) network environment, or as a server or a client machine ina cloud computing infrastructure or environment.

The machine can be a personal computer (PC), a tablet PC, a set-top box(STB), a Personal Digital Assistant (PDA), a cellular telephone, a webappliance, a server, a network router, a switch or bridge, or anymachine capable of executing a set of instructions (sequential orotherwise) that specify actions to be taken by that machine. Further,while a single machine is illustrated, the term “machine” shall also betaken to include any collection of machines that individually or jointlyexecute a set (or multiple sets) of instructions to perform any one ormore of the methodologies discussed herein.

The example computer system 500 includes a processing device 502, a mainmemory 504 (e.g., read-only memory (ROM), flash memory, dynamic randomaccess memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM(RDRAM), etc.), a static memory 506 (e.g., flash memory, static randomaccess memory (SRAM), etc.), and a data storage system 518, whichcommunicate with each other via a bus 530.

Processing device 502 represents one or more general-purpose processingdevices such as a microprocessor, a central processing unit, or thelike. More particularly, the processing device can be a complexinstruction set computing (CISC) microprocessor, reduced instruction setcomputing (RISC) microprocessor, very long instruction word (VLIW)microprocessor, or a processor implementing other instruction sets, orprocessors implementing a combination of instruction sets. Processingdevice 502 can also be one or more special-purpose processing devicessuch as an application specific integrated circuit (ASIC), a fieldprogrammable gate array (FPGA), a digital signal processor (DSP),network processor, or the like. The processing device 502 is configuredto execute instructions 526 for performing the operations and stepsdiscussed herein. The computer system 500 can further include a networkinterface device 508 to communicate over the network 520.

The data storage system 518 can include a machine-readable storagemedium 524 (also known as a computer-readable medium) on which is storedone or more sets of instructions 526 or software embodying any one ormore of the methodologies or functions described herein. Theinstructions 526 can also reside, completely or at least partially,within the main memory 504 and/or within the processing device 502during execution thereof by the computer system 500, the main memory 504and the processing device 502 also constituting machine-readable storagemedia. The machine-readable storage medium 524, data storage system 518,and/or main memory 504 can correspond to the memory sub-system 110 ofFIG. 1.

In one embodiment, the instructions 526 include instructions toimplement functionality corresponding to an error control component(e.g., the battery monitoring component 113 of FIG. 1). While themachine-readable storage medium 524 is shown in an example embodiment tobe a single medium, the term “machine-readable storage medium” should betaken to include a single medium or multiple media that store the one ormore sets of instructions. The term “machine-readable storage medium”shall also be taken to include any medium that is capable of storing orencoding a set of instructions for execution by the machine and thatcause the machine to perform any one or more of the methodologies of thepresent disclosure. The term “machine-readable storage medium” shallaccordingly be taken to include, but not be limited to, solid-statememories, optical media, and magnetic media.

Some portions of the preceding detailed descriptions have been presentedin terms of algorithms and symbolic representations of operations ondata bits within a computer memory. These algorithmic descriptions andrepresentations are the ways used by those skilled in the dataprocessing arts to most effectively convey the substance of their workto others skilled in the art. An algorithm is here, and generally,conceived to be a self-consistent sequence of operations leading to adesired result. The operations are those requiring physicalmanipulations of physical quantities. Usually, though not necessarily,these quantities take the form of electrical or magnetic signals capableof being stored, combined, compared, and otherwise manipulated. It hasproven convenient at times, principally for reasons of common usage, torefer to these signals as bits, values, elements, symbols, characters,terms, numbers, or the like.

It should be borne in mind, however, that all of these and similar termsare to be associated with the appropriate physical quantities and aremerely convenient labels applied to these quantities. The presentdisclosure can refer to the action and processes of a computer system,or similar electronic computing device, that manipulates and transformsdata represented as physical (electronic) quantities within the computersystem's registers and memories into other data similarly represented asphysical quantities within the computer system memories or registers orother such information storage systems.

The present disclosure also relates to an apparatus for performing theoperations herein. This apparatus can be specially constructed for theintended purposes, or it can include a general purpose computerselectively activated or reconfigured by a computer program stored inthe computer. Such a computer program can be stored in a computerreadable storage medium, such as, but not limited to, any type of diskincluding floppy disks, optical disks, CD-ROMs, and magnetic-opticaldisks, read-only memories (ROMs), random access memories (RAMs), EPROMs,EEPROMs, magnetic or optical cards, or any type of media suitable forstoring electronic instructions, each coupled to a computer system bus.

The algorithms and displays presented herein are not inherently relatedto any particular computer or other apparatus. Various general purposesystems can be used with programs in accordance with the teachingsherein, or it can prove convenient to construct a more specializedapparatus to perform the method. The structure for a variety of thesesystems will appear as set forth in the description below. In addition,the present disclosure is not described with reference to any particularprogramming language. It will be appreciated that a variety ofprogramming languages can be used to implement the teachings of thedisclosure as described herein.

The present disclosure can be provided as a computer program product, orsoftware, that can include a machine-readable medium having storedthereon instructions, which can be used to program a computer system (orother electronic devices) to perform a process according to the presentdisclosure. A machine-readable medium includes any mechanism for storinginformation in a form readable by a machine (e.g., a computer). In someembodiments, a machine-readable (e.g., computer-readable) mediumincludes a machine (e.g., a computer) readable storage medium such as aread only memory (“ROM”), random access memory (“RAM”), magnetic diskstorage media, optical storage media, flash memory components, etc.

In the foregoing specification, embodiments of the disclosure have beendescribed with reference to specific example embodiments thereof. Itwill be evident that various modifications can be made thereto withoutdeparting from the broader spirit and scope of embodiments of thedisclosure as set forth in the following claims. The specification anddrawings are, accordingly, to be regarded in an illustrative senserather than a restrictive sense.

What is claimed is:
 1. A system comprising: a memory component of amemory sub-system; and a processing device, operatively coupled with thememory component, to: determine that an amount of invalid data on afirst data block stored on the memory component satisfies a thresholdlevel for attempting to perform a garbage collection operation for thefirst data block, the garbage collection operation for the first datablock comprising a migration of one or more pages of the first datablock that contain valid data to a second data block stored on thememory component; upon determining that the amount of invalid data onthe first data block satisfies the threshold level, determine whether abattery life state of a battery associated with the memory sub-system isbelow a first battery life threshold; upon determining that the batterylife state is below the first battery life threshold, postpone thegarbage collection operation for the first data block; upon postponingthe garbage collection operation for the data block, monitor the batterylife state to determine whether the battery life state changes to beequal to or above a second battery life threshold; and upon determiningthat the battery life state changes to be equal to or above the secondbattery life threshold, perform the garbage collection operation for thefirst data block.
 2. The system of claim 1, wherein the first batterylife threshold is same as the second battery life threshold.
 3. Thesystem of claim 1, wherein the first battery life threshold is differentfrom the second battery life threshold.
 4. The system of claim 1,wherein the first threshold level corresponds to a threshold amount ofdata that indicates that the garbage collection operation can beoptionally performed for the first data block.
 5. The system of claim 1,wherein the processing device is further to, prior to determining thatthe battery life state changes to be equal to or greater than the secondbattery life threshold: determine that the amount of invalid data on thefirst data block satisfies a second threshold level to perform thegarbage collection operation for the first data block, wherein thesecond threshold level indicates that the garbage collection operationfor the first data block must be performed; and responsive todetermining that amount of invalid data on the first data blocksatisfies the second threshold level perform the garbage collectionoperation for the first data block.
 6. The system of claim 1, furthercomprising: a battery sensor to detect the battery life state.
 7. Thesystem of claim 1, further comprising: a value comparator to perform acomparison operation between two or more values of the battery todetermine whether the battery life state is at least one of: below thefirst battery life threshold or equal to or above the second batterylife threshold.
 8. A method comprising: determining, by a processingdevice, that an amount of invalid data on a first data block stored on amemory component of a memory sub-system satisfies a threshold level forattempting to perform a garbage collection operation for the first datablock, the garbage collection operation for the first data blockcomprising a migration of one or more pages of the first data block thatcontain valid data to a second data block stored on the memorycomponent; responsive to determining that the amount of invalid data onthe data block satisfies the threshold level, monitoring, by theprocessing device, a battery life state of a battery associated with thememory sub-system to determine whether the battery life state is equalto or above a battery life threshold; and responsive to determining thatthe battery life state is equal to or above the battery life threshold,performing, by the processing device, the garbage collection operationfor the first data block.
 9. The method of claim 8, further comprising:responsive to determining that the battery life state is below thebattery life threshold, continuing, by the processing device, to monitorthe battery life state to determine whether the battery life statechanges to be equal to or above a second battery life threshold; andresponsive to determining that the battery life state changes to beequal or above the second battery life threshold, performing, by theprocessing device, the garbage collection operation for the first datablock.
 10. The method of claim 9, wherein the battery life threshold issame as the second battery life threshold.
 11. The method of claim 9,wherein the battery life threshold is different from the second batterylife threshold.
 12. The method of claim 9, further comprising, prior todetermining that the battery life state changes to be equal to orgreater than the second battery life threshold: determining, by theprocessing device, that the amount of invalid data on the first datablock satisfies a second threshold level to perform the garbagecollection operation for the first data block, wherein the secondthreshold level indicates that the garbage collection operation for thefirst data block must be performed; and responsive to determining thatamount of invalid data on the first data block satisfies the secondthreshold level, performing, by the processing device, the garbagecollection operation for the first data block.
 13. The method of claim8, wherein the threshold level corresponds to a threshold amount of datathat indicates that the garbage collection operation can be optionallyperformed for the first data block.
 14. The method of claim 8, whereinmonitoring the battery life state comprises receiving the battery lifestate from a battery sensor.
 15. The method of claim 8, whereinmonitoring the battery life state comprises receiving, from a valuecomparator, a comparison operation between two or more values of thebattery to determine whether the battery life state equal to or abovethe battery life threshold.
 16. A non-transitory computer-readablestorage medium comprising instructions that, when executed by aprocessing device, cause the processing device to: determine that anamount of invalid data on a first data block stored on a memorycomponent of a memory sub-system satisfies a threshold level forattempting to perform a garbage collection operation for the first datablock, the garbage collection operation for the first data blockcomprising a migration of one or more pages of the first data block thatcontain valid data to a second data block stored on the memorycomponent; upon determining that the amount of invalid data on the firstdata block satisfies the threshold level, determine whether a batterylife state of a battery associated with the memory sub-system is below afirst battery life threshold; upon determining that the battery lifestate is below the first battery life threshold, postpone the garbagecollection operation for the first data block; determine whether thebattery life state changes to be equal to or above a second battery lifethreshold; and upon determining that the battery life state changes tobe equal to or above the second battery life threshold, perform thegarbage collection operation for the first data block.
 17. Thenon-transitory computer-readable storage medium of claim 16, wherein thefirst battery life threshold is same as the second battery lifethreshold.
 18. The non-transitory computer-readable storage medium ofclaim 16, wherein the first battery life threshold is different from thesecond battery life threshold.
 19. The non-transitory computer-readablestorage medium of claim 16, wherein the threshold level corresponds to athreshold amount of data that indicates that the garbage collectionoperation for the first data block can be optionally performed.
 20. Thenon-transitory computer-readable storage medium of claim 16, wherein theprocessing device is further to, prior to determining that the batterylife state changes to be equal to or greater than the second batterylife threshold: determine that the amount of invalid data on the firstdata block satisfies a second threshold level to perform the garbagecollection operation for the first data block, wherein the secondthreshold level indicates that the garbage collection operation for thefirst data block must be performed; and responsive to determining thatamount of invalid data on the first data block satisfies the secondthreshold level, perform the garbage collection operation for the firstdata block.